Memory with a memory cell comprising a selection transistor and a memory capacitor and method for production thereof

ABSTRACT

A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling, on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substrate, with a selectively grown epitaxial layer. The selection transistor is formed in the selectively grown epitaxial layer, comprises a source region connected to the trench capacitor, and a drain region connected to a bit line. The junction depth of the source region is now chosen so that the source region reaches as far as the insulating covering layer. Optionally, the thickness of the epitaxial layer can be reduced to a thickness by oxidation and a subsequent etching. Afterwards, a contact trench is etched through the source region down to the conductive trench filling, which trench is filled with a conductive contact and electrically connects the conductive trench filling to the source region.

[0001] Memory having a memory cell, comprising a selection transistorand a storage capacitor, and method for fabricating it

[0002] The present application relates to a memory having a memory cell,comprising a selection transistor and a storage capacitor, and to amethod for fabricating it.

[0003] The present invention is explained with regard to a DRAM memorycell of a semiconductor memory. For discussion purposes, the inventionis described in respect of the formation of an individual memory cell.

[0004] Integrated circuits (ICs) or chips contain capacitors for thepurpose of storing charge, such as, for example, a dynamic random accessmemory (DRAM). In this case, the charge state in the capacitorrepresents a data bit.

[0005] A DRAM chip contains a matrix of memory cells which are arrangedin the form of rows and columns and are addressed by word lines and bitlines. The reading of data from the memory cells or the writing of datato the memory cells is realized by activating suitable word lines andbit lines.

[0006] A DRAM memory cell usually contains a transistor connected to acapacitor. The transistor is referred to as a selection transistor andcomprises, inter alia, two doping regions isolated from one another by achannel which is controlled by a gate. Depending on the direction ofcurrent flow, one doping region is referred to as the drain region andthe other as the source region. The source region is connected forexample to the trench capacitor, the drain region is connected to a bitline and the gate is connected to a word line. By the application ofsuitable voltages to the gate, the transistor is controlled in such away that a current flow between the source region and the drain regionthrough the channel is switched on and off.

[0007] The charge stored in the capacitor decreases over time on accountof leakage currents. Before the charge has decreased to a level below athreshold value, the storage capacitor must be refreshed. For thisreason, these memories are referred to as dynamic RAM (DRAM).

[0008] The central problem in known DRAM variants based on a trenchcapacitor is the production of a sufficiently large capacitance for thetrench capacitor. This problem will be aggravated in future by theadvancing miniaturization of semiconductor components. The increase inthe integration density means that the area available per memory celland thus the capacitance of the trench capacitor decrease ever further.

[0009] Sense amplifiers require a sufficient signal level for reliablyreading out the information situated in the memory cell. The ratio ofthe storage capacitance to the bit line capacitance is crucial indetermining the signal level. If the storage capacitance is too low,said ratio may be too small for generating an adequate signal.

[0010] A lower storage capacitance likewise requires a higher refreshfrequency, because the quantity of charge stored in the trench capacitoris limited by its capacitance and additionally decreases due to leakagecurrents. If the quantity of charge falls below a minimum quantity ofcharge in the storage capacitor, then it is no longer possible for theinformation stored therein to be read out by a connected senseamplifier, the information is lost and read errors arise.

[0011] One way of avoiding read errors is to reduce the leakagecurrents. Leakage currents can be reduced on the one hand by transistorsand on the other hand by dielectrics, such as the capacitor dielectric,for example. An undesirably reduced retention time can be lengthened bythese measures.

[0012] Stacked capacitors or trench capacitors are usually used inDRAMs. In this case, a trench capacitor has a three-dimensionalstructure which is formed in a silicon substrate, for example. Anincrease in the capacitor electrode area and thus in the capacitance ofthe trench capacitor can be achieved for example by etching more deeplyinto the substrate and thus by deeper trenches. In this case, theincrease in the capacitance of the trench capacitor does not cause thesubstrate surface occupied by the memory cell to be enlarged. However,this method is also limited, since the attainable etching depth of thetrench capacitor depends on the trench diameter, and, duringfabrication, it is only possible to attain specific, finite aspectratios between the trench depth and trench diameter.

[0013] As the increase in the integration density advances, thesubstrate surface available per memory cell decreases ever further. Theassociated reduction in the trench diameter leads to a reduction in thecapacitance of the trench capacitor. If the capacitance of the trenchcapacitor is dimensioned to be so low that the charge which can bestored is insufficient for entirely satisfactory read out by the senseamplifiers connected downstream, then this results in read errors.

[0014] This problem is explained for example in the document DE 199 41148, the selection transistor, which is usually arranged next to thetrench capacitor, being arranged above the trench capacitor. As aresult, the trench of the trench capacitor can take up a part of thesubstrate surface which was conventionally reserved for the transistor.Through this arrangement, the trench capacitor and the transistor sharepart of the substrate surface. This arrangement is made possible by anepitaxial layer grown above the trench capacitor.

[0015] What is problematic, however, is the electrical connection of thetrench capacitor to the transistor. Purely lithographic methods forfabricating the electrical connection require a minimum distance betweenthe trench capacitor and the transistor for the lithographic alignmentof the individual lithographic planes with respect to one another.Through purely lithographic methods, the memory cells in the memory cellarray require a relatively large area and are unsuitable for integrationin a large-scale integrated cell array.

[0016] What is disadvantageous about the memory cells known from theprior art is that the resistance of the electrical connection betweenthe trench capacitor and the source region of the transistor has arelatively large value, which slows down the access to the memory cell.

[0017] A further disadvantage of the prior art is that a sufficientretention time is only achieved by complex insulation measures whichrequire a large number of processing steps. In this case, the electricalcontact is insulated from the substrate in a complex manner.

[0018] The object of the present invention is to specify a memory havinga memory cell, comprising a selection transistor and a storagecapacitor, and a method for fabricating it in which the retention timeis improved.

[0019] With regard to the memory, the object is achieved by means of amemory having a memory cell, comprising:

[0020] a substrate having a substrate surface and a trench, in which isarranged a trench capacitor filled with a conductive trench filling, onwhich an insulating covering layer is arranged in the trench;

[0021] a selectively grown epitaxial layer, which, proceeding from thesubstrate surface, extends laterally over the insulating covering layerand is arranged on the substrate surface and the insulating coveringlayer;

[0022] a selection transistor, which comprises a source region, a drainregion, a gate oxide and a gate electrode, the source region and thedrain region being arranged in the epitaxial layer and the gate oxidebeing arranged on the epitaxial layer and the source region extendingfrom a surface of the epitaxial layer that is remote from the substrateas far as the insulating covering layer;

[0023] a conductive contact, which is arranged in a contacttrench—arranged in the epitaxial layer and the insulating coveringlayer—on the conductive trench filling and connects the source region tothe conductive trench filling.

[0024] The source region extends from the surface of the epitaxial layeras far as the insulating covering layer, so that a pn junction isarranged here between the doping of the source region, on the one hand,and of the channel region and of the bulk region, on the other hand,which pn junction prevents an uncontrolled current flow and leakagecurrents. The current flow through the channel can be controlled bymeans of the gate electrode, so that the transistor can be switched onand off in a defined manner. Furthermore, it is advantageous that, inthe memory according to the invention, complex insulation of theconductive contact can be dispensed with since leakage currents arealready avoided by the advantageous configuration of the source region.Consequently, it is possible to form the conductive contact between thesource region and the conductive trench filling with an enlargedcross-sectional area, which enables a lower contact resistance.Consequently, the speed of the memory cell and of the memory is alsoimproved.

[0025] The doping for the source region and the doping for the drainregion can be introduced into the epitaxial layer in two separateprocess steps, so that the source region can be formed for example witha significantly larger junction depth than the drain region. The planarjunction depth of the source region is advantageous since it avoids afloating body effect, since the substrate is connected to the channel ofthe transistor with the substrate. Furthermore, an improved overlaytolerance is made possible by the planar doped drain region, since thetransistor, with a drain region formed in a correspondingly planarmanner, can also be arranged entirely above the trench capacitor and thefloating body effect is nevertheless avoided.

[0026] The additional collar insulation in the lower region of theconductive contact, which collar insulation is known from the prior artand is absolutely necessary therein, can thus be obviated. This is madepossible by the variation of the doping profile of the source region.Thus, by way of example, the junction depth of the source region ischosen in such a way that it reaches as far as the insulating coveringlayer. The process steps required from the prior art, such as thedeposition of a CVD insulation collar (Chemical Vapour Deposition), thesubsequent plasma etching for patterning the insulation collar, achemical cleaning, the deposition of an arsenic-doped polycrystallinesilicon, the plasma etching and a further wet etching, can thus beobviated. Consequently, a reduction in costs also results for the memoryaccording to the invention in comparison with memories known from theprior art.

[0027] One refinement of the invention provides for the gate electrodeto be arranged on the epitaxial layer and at least partly to cover thetrench. This arrangement has the advantage that the selection transistorcan be arranged in a space-saving manner above the trench capacitor, inthe epitaxial layer, so that the individual memory cells are arrangedwith a reduced space requirement.

[0028] A further refinement of the memory cell according to theinvention provides for a trench isolation, proceeding from the surfaceof the epitaxial layer that is remote from the substrate, to reach intothe substrate—beyond the insulating covering layer—in order to isolateadjacent memory cells from one another.

[0029] The trench isolation is usually referred to as STI (ShallowTrench Isolation) and in this case is formed in such a way that,proceeding from the surface of the epitaxial layer that is remote fromthe substrate, it reaches through the epitaxial layer at least as far asthe insulating covering layer. In this case, the trench isolation canperfectly well be introduced more deeply into the substrate and, forexample, occupy part of the space originally taken up by the trench ofthe trench capacitor. Thus, the STI replaces part of the trench and ofthe conductive trench filling with an insulation material.

[0030] A further refinement of the memory cell according to theinvention provides for a second gate electrode to be arranged as passingword line on the trench isolation and for the contact trench to bearranged between the first gate electrode and the second gate electrodewith the conductive contact situated therein. The arrangement of thecontact trench between the first gate electrode and the second gateelectrode enables the contact trench to be formed in a self-alignedmanner between the first gate electrode and the second gate electrode.

[0031] A further refinement of the memory cell according to theinvention provides for the epitaxial layer to have a thickness ofbetween 25 nm and 100 nm, preferably between 40 nm and 80 nm. Anepitaxial layer having a layer thickness in the ranges specified has theadvantage that the junction depth of the source region can be formedaccording to the invention in such a way that the source region reachesas far as the insulating covering layer. The drain region is formed insuch a planar manner that a floating body effect is avoided. By way ofexample, for this purpose, the drain region can be formed with animplantation depth which approximately corresponds to half the thicknessof the epitaxial layer. This is likewise possible if the channel lengthof the selection transistor assumes a value of between 20 nm and 300 nm.

[0032] In this case, the epitaxial layer in which the selectiontransistor is arranged is formed with an improved uniformity.

[0033] A further refinement of the memory cell according to theinvention provides for an insulating encapsulation to be arranged on asurface of the first gate electrode that is remote from the substrateand on side areas adjoining said surface of said electrode. Theinsulating encapsulation has the advantage that it can be used as anetching mask for the self-aligned formation of the contact trench.Furthermore, it is possible to use the insulating encapsulation as aself-aligned etching mask for the formation of a bit line contact whichconnects the drain region to a bit line.

[0034] A further refinement of the memory cell according to theinvention provides for an intermediate layer to be arranged in thecontact trench between the conductive trench filling and the conductivecontact or between the conductive trench filling and the source regionfor the purpose of avoiding crystal dislocations or for the purpose ofcontrolling a diffusion. The intermediate layer may be configured forexample as a conductive layer. The intermediate layer may likewise beformed as an insulating layer which, however, is formed with such asmall thickness that a large tunnelling current can flow through it.Usually, the layer thickness is then at most two nanometers. Theintermediate layer has the advantage that crystal dislocations which arepossibly arranged in the conductive trench filling cannot be propagatedinto the selection transistor and, consequently, also cannot damage thesource region and the pn junction between source region and bulk region.Furthermore, the diffusion of dopant can be prevented by theintermediate layer, so that dopant originating from the conductivecontact is not added to the channel. Consequently, the intermediatelayer can reduce leakage currents.

[0035] With regard to the method, the object is achieved by means of amethod for fabricating a memory having a memory cell, which has aselection transistor having a source region, a drain region, a gateoxide and a gate electrode, and also a trench capacitor having an innerelectrode, an outer electrode and an insulating layer arranged inbetween, having the steps of:

[0036] providing a substrate with a trench;

[0037] filling the trench with a conductive trench filling for thepurpose of forming the inner electrode of the trench capacitor;

[0038] forming an insulating covering layer on the conductive trenchfilling;

[0039] growing an epitaxial layer on the substrate, the epitaxial layergrowing laterally, proceeding from the substrate, over the insulatingcovering layer, so that the epitaxial layer at least partly covers theinsulating covering layer;

[0040] forming a trench isolation in the epitaxial layer for the purposeof isolating adjacent memory cells;

[0041] forming the first gate electrode on the epitaxial layer and asecond gate electrode for a passing word line on the trench isolation;

[0042] introducing dopant for the purpose of forming the source regionand the drain region, a predetermined thickness of the epitaxial layerand the doping being chosen in such a way that the source region reachesfrom the surface of the epitaxial layer that is remote from thesubstrate as far as the insulation layer;

[0043] etching a contact trench between the first gate electrode and thesecond gate electrode, the epitaxial layer and the insulating coveringlayer being removed from the region between the first gate electrode andthe second gate electrode and the conductive trench filling beinguncovered;

[0044] introducing a conductive contact into the contact trench for thepurpose of electrically connecting the source region to the conductivetrench filling.

[0045] In an advantageous manner, the source region is in this caseformed with a junction depth which reaches as far as the insulatingcovering layer. As already explained in connection with the claimedmemory, this improves the memory behaviour and the retention time of thememory and also reduces the resistance of the conductive contact to theelectrical connection of the conductive trench filling to the sourceregion.

[0046] An advantageous refinement of the method according to theinvention provides for the epitaxial layer to be thinned to apredetermined thickness. This is advantageous since the epitaxial layercan thus be reduced to a thickness which is smaller than the sourceregion junction depth used, so that the source region reaches as far asthe insulating covering layer.

[0047] During the formation of the epitaxial layer, the epitaxial layeris grown laterally proceeding from the substrate over the insulatingcovering layer situated in the trench. In order to completely cover theinsulating covering layer, the selective epitaxial layer is formed witha thickness which is greater than half the diameter of the trench. Sincethis thickness can perfectly well be larger than an expedient junctiondepth of the source region of the selection transistor, the epitaxiallayer is subsequently correspondingly thinned.

[0048] An advantageous refinement of the method according to theinvention provides for the epitaxial layer to be thinned to a thicknessof between 25 nm and 100 nm, preferably to a thickness of between 40 nmand 80 nm. The specified thicknesses for the epitaxial layer areadvantageously suited to the fact that the junction depth of the sourceregion can be formed through the entire epitaxial layer and reaches asfar as the insulating covering layer.

[0049] A further advantageous refinement of the method according to theinvention provides for the epitaxial layer, in order to be thinned, tobe partly oxidized to form an oxide layer and the oxide layer to beremoved selectively with respect to the remainder of the epitaxiallayer.

[0050] A further advantageous variant of the method according to theinvention provides for the epitaxial layer to be thinned by means ofchemical mechanical polishing. Chemical mechanical polishing (CMP) islikewise suitable for thinning the epitaxial layer. In this case,however, it must be taken into account that at least a further thinningby means of an oxidation should be carried out since a surface polishedby means of CMP is greatly roughened and should be improved if a channelof a transistor is arranged in this surface.

[0051] A further advantageous refinement of the method according to theinvention provides for the oxidation of the epitaxial layer to becarried out as wet oxidation at a temperature of between 900° C. and1100° C. A wet oxidation is suitable for oxidizing the epitaxial layerfor example on account of the sufficient speed for the formation of theoxide layer.

[0052] A further method variant provides for the oxidation to be carriedout in an atmosphere containing hydrogen peroxide and hydrogen. Theaforementioned atmosphere is suitable for a wet oxidation, for example.

[0053] A further advantageous refinement of the method according to theinvention provides for the oxide layer to be removed wet-chemically.

[0054] The method according to the invention is developed to the effectthat the surface of the conductive trench filling that is uncoveredafter the etching of the contact trench is cleaned, the surface beingoxidized and the oxide layer formed in the process being removed. Thecleaning of the conductive trench filling has the advantage that it ispossible to form an electrical contact with a reduced contact resistancebetween the conductive trench filling and the subsequently formedconductive contact.

[0055] A further refinement of the method according to the inventionprovides for the conductive contact to be formed by means of a selectivedeposition. A selective deposition can be carried out for example as aselective silicon deposition, the grown silicon growing only on silicon,such as, for example, monocrystalline silicon or polycrystallinesilicon. The selectivity is established in the fact that the grownsilicon does not grow for example on a silicon oxide layer, a siliconnitride layer or other materials. The selectivity of the deposition canbe set for example by suitable process parameters.

[0056] The respective subclaims relate to further advantageousrefinements of the invention.

[0057] The invention is explained in more detail below with reference toexemplary embodiments and figures.

[0058] In the figures:

[0059]FIG. 1 shows a sectional diagram of a memory cell according to theinvention;

[0060]FIG. 2 shows the plan view of a memory cell array of the memoryaccording to the invention;

[0061]FIG. 3 shows a substrate with a selectively grown epitaxial layer;

[0062]FIG. 4 shows the substrate from FIG. 3, the selective epitaxiallayer having been at least partly converted into an oxide layer;

[0063]FIG. 5 shows the substrate from FIG. 4, the oxide layer havingbeen removed;

[0064]FIG. 6 shows the substrate from FIG. 5, two selection transistorshaving been formed in—and on—the epitaxial layer;

[0065]FIG. 7 shows the substrate from FIG. 6, a contact trench havingbeen formed;

[0066]FIG. 8 shows the substrate from FIG. 7, a conductive contacthaving been formed in the contact trench.

[0067]FIG. 1 illustrates a memory cell 10 of a memory 5 in a substrate15 in a sectional diagram. A trench 25 is arranged in the substrate 15,which has a substrate surface 20. A trench capacitor 30 is formed as astorage capacitor in the trench 25. The storage capacitor comprises aninner electrode 130, an outer electrode 135 and an insulating layer 140arranged between the inner electrode 130 and the outer electrode 135.The inner capacitor electrode 130 is formed for example by theconductive trench filling 35 arranged in the trench 25.

[0068] An insulating covering layer 40 is arranged on the conductivetrench filling 35 in the trench 25. A selectively grown epitaxial layer45 is arranged on the substrate 15 and the insulating covering layer 40.The selectively grown epitaxial layer 45 has a thickness 50. Thethickness 50 corresponds for example to a predetermined thickness 55.

[0069] A selection transistor 60 is arranged in the selectively grownepitaxial layer 45, said transistor comprising a source region 65, adrain region 70, a gate oxide 75 and a first gate electrode 80. Arrangedon the first gate electrode 80 is a conductive layer 81, which issuitable for configuring the arrangement comprising gate electrode 0.80and conductive layer 81 as a low-resistance word line. The gate oxide 75and the first gate electrode 80 are arranged on the surface 85 of theepitaxial layer 45 that is remote from the substrate.

[0070] A trench isolation 100 is arranged beside the epitaxial layer 45,in the substrate 15. The trench isolation 100 extends into the substrate15 from the surface 85 that is remote from the substrate, the trenchisolation 100 occupying at least part of the volume originally taken upby the trench 25. A second gate electrode 105 is arranged on the trenchisolation 100. The second gate electrode 105 is part of a passing wordline which is provided for addressing adjacent memory cells.

[0071] An insulating encapsulation 125 is arranged on the surface of thefirst gate electrode 115 that is remote from the substrate and theadjoining side areas 120. The insulating encapsulation 125 is suitablefor example for forming a contact trench 95 in which the conductivecontact 90 is arranged.

[0072] An intermediate layer 145 is optionally arranged between theconductive contact 90 and the conductive trench filling 35. Theintermediate layer 145 may likewise optionally be arranged between theconductive contact 90 and the source region 65. In this case, theconductive contact 90 serves for electrically connecting the sourceregion 65 to the conductive trench filling 35. An insulation collar 155is arranged in the upper region of the trench 25.

[0073] In order to make contact with the outer electrode 135 of thetrench capacitor 30, a buried well 160 is introduced into the substrate15. The insulation collar 155 serves for avoiding leakage currentsbetween the outer electrode 135 through the substrate 15 to the sourceregion 65 or the drain region 70. On the drain region 70, a bit linecontact 165 is arranged on the surface 85 of the epitaxial layer 45 thatis remote from the substrate, beside the first gate electrode 80.

[0074] The substrate is formed for example from lightly p-doped siliconand is of monocrystalline configuration. The conductive trench fillingcomprises, for example, doped polycrystalline silicon. The insulatingcovering layer 40 is formed for example from silicon oxide and couldlikewise comprise silicon nitride. The selectively grown epitaxial layeris likewise formed from silicon or lightly p-doped silicon, in a mannercorresponding to the substrate. The source region 65 and the drainregion 70 are formed with a high dopant concentration, the doping of thesource region 65 and of the drain region 70 having the opposite polarityto the doping of the substrate. The gate oxide is formed for examplefrom silicon oxide or nitrided silicon oxide. The first gate electrode80 comprises, for example, doped polycrystalline silicon, and theconductive layer 81 contains, for example, a metal or a metal silicideor a metal nitride such as tungsten or titanium silicide or molybdenumsilicide or tungsten silicide or tungsten nitride or titanium nitride ortantalum silicide or tantalum nitride.

[0075] The conductive contact 90 is formed for example from highly dopedpolycrystalline silicon. The trench isolation 100 comprises, forexample, doped or undoped silicon oxide. The passing word line 110 withthe second gate electrode 105 is formed in a manner corresponding to thefirst gate electrode 80 with the conductive layer 81. The insulatingencapsulation 125 comprises silicon nitride, for example. The innerelectrode 130 of the capacitor 30 corresponds to the conductive trenchfilling 35, and the outer electrode 135 of the trench capacitor 30 isformed for example by means of a doping into the substrate 115 aroundthe lower region of the trench capacitor 30. The insulating layer 140 ofthe trench capacitor 30 comprises, for example, silicon oxide, siliconnitride or silicon oxynitride.

[0076] The intermediate layer 145 is formed for example from a metalsilicide or a metal nitride or silicon nitride. By way of example,titanium silicide or molybdenum silicide or tungsten silicide ortantalum silicide are suitable as metal silicide. By way of example,titanium nitride or tungsten nitride or tantalum nitride is suitable asmetal nitride. The insulation collar 155 comprises, for example, siliconoxide or silicon nitride. The bit line contact 165 comprises a metal,for example.

[0077] A plan view of a memory cell array of a memory 5 is illustratedwith reference to FIG. 2. The arrangement illustrated in FIG. 1 is, forexample, a sectional diagram along the sectional line A from FIG. 2. Thememory cell 10 comprises the trench 25, the conductive contact 90, thebit line contact 165 and also the selectively grown epitaxial layer 45.The memory cell is isolated from adjacent memory cells by means of thetrench isolation 100. In this case, the first gate electrode 80 runsover the epitaxial layer 45. The first gate electrode 80 is lined withthe insulating encapsulation 125. The passing word line 110 runsadjacent to the first gate electrode 80.

[0078] A method for fabricating the memory cell 10 illustrated in FIG. 1is described with reference to FIGS. 3 to 8.

[0079]FIG. 3 illustrates the substrate 15, in which the trench 25 isarranged. In the upper region of the trench 25 illustrated, theinsulation collar 155 is arranged at the sidewall of the trench 25 andthe trench 25 is filled with the conductive trench filling 35. Theinsulating covering layer 40 is arranged in the trench 25, on theconductive trench filling 35. Afterwards, the epitaxial layer 45 isgrown selectively, proceeding from the substrate surface 20, the trench25 and the insulating layer 40 which covers the trench being laterallyovergrown. The lateral overgrowth takes place for example simultaneouslyfrom all sides. In this case, the selective epitaxial layer 45 is formedfor example with a thickness of approximately 300 nm.

[0080] Afterwards, the epitaxial layer 45 formed is thermally oxidized,the epitaxial layer 45 being at least partly converted into an oxidelayer 150. The oxidation can be carried out for example as a so-calledwet oxidation, a wet oxidation usually being characterized by the factthat hydrogen peroxide and hydrogen are present in the atmospheresurrounding the substrate during the oxidation. The wet oxidation can becarried out for example at a temperature of between 900° C. and 1100°C., such as 1000° C. for example, for a time duration of 110 minutes,for example. In this case, an oxide layer having a thickness ofapproximately 570 nm is typically formed, and the residual height of theepitaxial layer 45 is now about 50 nm, given an epitaxial layerinitially having a thickness of 300 nm. During this process, the mixtureratio between hydrogen peroxide to hydrogen can be set to 1.67, forexample.

[0081] With reference to FIG. 5, the oxide layer 150 is subsequentlyremoved wet-chemically and a cleaning step is optionally carried out onthe uncovered surface 85 of the epitaxial layer 45.

[0082] With reference to FIG. 6, the trench isolation 100 issubsequently etched into the epitaxial layer 45, the substrate 15 andthe trench capacitor 30 and filled with an insulating material such assilicon oxide, for example. Afterwards, the first gate electrode 80 andthe second gate electrode 105 are formed, in this exemplary embodiment apolycrystalline layer and a conductive layer arranged thereon beingdeposited and patterned together, the first gate electrode 80 beingformed together with the conductive layer 81 and the passing word line110 being formed adjacent thereto.

[0083] Afterwards, dopant is introduced into the epitaxial layer 45, thesource region 65 and the drain region 70 being formed. The formation ofthe insulating encapsulation 125 is optionally provided, whichencapsulation can also be formed, for example, between two doping stepsfor the formation of the source region 65 and of the drain region 70. Inthis case, the source region 65 is formed to such a depth into theepitaxial layer 45 that it reaches as far as the insulating coveringlayer 40.

[0084] Afterwards, by way of example, a BPSG (borophosphorus silicateglass) layer is deposited for planarization purposes and aphotosensitive mask 170 is deposited thereon. The photosensitive mask isexposed and patterned, so that the contact trench 95 can be formedbetween the first gate electrode 80 and the second gate electrode 105.What is advantageous in this case is that the contact trench 95 can beformed selectively with respect to the insulating encapsulation 125.This advantageously has the result that the formation of the contacttrench 95 can be carried out in a self-aligned manner.

[0085] With reference to FIG. 7, the epitaxial layer 45 and theinsulating covering layer 40 are removed in the region of the contacttrench, so that the conductive trench filling 35 is uncovered.

[0086] With reference to FIG. 8, the conductive contact 90 issubsequently formed in the contact trench 95, so that the conductivetrench filling 35 is electrically connected to the source region 65.

[0087] The further method steps which are suitable for forming the bitline contact are carried out in accordance with the methods known fromthe prior art.

[0088] After the application of a selective epitaxial layer having athickness of approximately 300 nm for the purpose of overgrowing thetrench capacitor, the epitaxial layer, in contrast to methods known fromthe prior art, is partly removed again by means of oxidation andsubsequent etching of the oxide layer formed. As a result, the verticalextent of the conductive contact 90 is reduced from formerlyapproximately 300 nm to now approximately 50 nm. After the removal ofthe insulating covering layer 40 and uncovering of the conductive trenchfilling 35 and an optional cleaning, the conductive contact 90 cansubsequently be formed by means of deposition. This enables an enormoussimplification of the connection of the source region 65 to theconductive trench filling 35.

[0089] List of reference symbols

[0090]5 Memory

[0091]10 Memory cell

[0092]15 Substrate

[0093]20 Substrate surface

[0094]25 Trench

[0095]30 Trench capacitor, storage capacitor

[0096]35 Conductive trench filling

[0097]40 Insulating covering layer

[0098]45 Selectively grown epitaxial layer

[0099]50 Thickness of the epitaxial layer

[0100]55 Predetermined thickness

[0101]60 Selection transistor

[0102]65 Source region

[0103]70 Drain region

[0104]75 Gate oxide

[0105]80 First gate electrode

[0106]81 Conductive layer

[0107]85 Surface of the epitaxial layer that is remote from thesubstrate

[0108]90 Conductive contact

[0109]95 Contact trench

[0110]100 Trench isolation

[0111]105 Second gate electrode

[0112]110 Passing word line

[0113]115 Surface of the first gate electrode that is remote from thesubstrate

[0114]120 Adjoining side area

[0115]125 Insulating encapsulation

[0116]130 Inner electrode of the trench capacitor

[0117]135 Outer electrode of the trench capacitor

[0118]140 Insulating layer

[0119]145 Intermediate layer

[0120]150 Oxide layer

[0121]155 Insulation collar

[0122]160 Buried well

[0123]165 Bit line contact

[0124]170 Mask

[0125] A Sectional line with respect to FIG. 1

1. A semiconductor memory having a memory cell, comprising: a substratehaving a substrate surface and a trench, the trench having a trenchcapacitor arranged therein the trench capacitor being filled with aconductive trench fillings: an insulating covering layer being arrangedin the trench; a selectively grown epitaxial layer, proceeding from thesubstrate surface the epitaxial layer extending laterally over theinsulating covering layer and is, the epitaxial layer being arranged onthe substrate surface and the insulating covering layer, a contacttrench being formed in the epitaxial layer and in the insulatingcovering layer the epitaxial layer having a sidewall along the contacttrench; a selection transistor the selection transistor including asource region, a drain region, a gate oxide and a gate electrode, thesource region and the drain region being arranged in the epitaxiallayer, the gate oxide being arranged on the epitaxial layers, and thesource region extending from a surface of the epitaxial layer that isremote from the substrate as far as the insulating covering layer; aconductive contact, which is the conductive contact being arranged inthe contact trench and on the conductive trench filling, the conductivecontact connecting the source region to the conductive trench filling, aconductive connection being formed along a length of the sidewall of theepitaxial layer, the length extending from the end of the sidewallformed at the covering layer as far as the upper end of the conductivecontact.
 2. The semiconductor memory according to claim 1, wherein thegate electrode is arranged on the epitaxial layer, the gage electrode atleast partly covering the trench.
 3. The semiconductor memory accordingto claim 1, wherein characterized in that a trench isolation, proceedingfrom the surface of the epitaxial layer that is remote from thesubstrate, reaches into the substrate (14) beyond the insulatingcovering layer in order to isolate adjacent memory cells from oneanother.
 4. The semiconductor memory according to claim 3, wherein asecond gate electrode is arranged as a passing word line on the trenchisolations, the contact trench is arranged between the first gateelectrode and the second gate electrode with the conductive contactsituated therein.
 5. The ssemiconductor memory according to claim 1 theepitaxial layer has a thickness of between 25 nm.
 6. The semiconductormemory according to claim 1 an insulating encapsulation is arranged on asurface of the first gate electrode that is remote from the substrateand on side areas adjoining the surface of the electrode.
 7. Thesemiconductor memory according to claim 1, wherein an intermediate layeris formed in the contact trench between the conductive trench fillingand the conductive contact from a conductive material, having athickness of up to 2 nanometres, thereby enabling a tunnelling currentthrough the intermediate layer.
 8. The semiconductor memory according toclaim 1, wherein an intermediate layer is formed in the contact trenchbetween the conductive contact and the source region from a conductivematerial, having a thickness of up to 2 nanometres, thereby enabling atunnelling current through the intermediate layer.
 9. The semiconductormemory according to claim 1, wherein the conductive contact touches thesidewall along the length.
 10. A method for fabricating a semiconductormemory having a memory cell, the semiconductor memory having a selectiontransistor, the selection transistor having a source region, a drainregion, a gate oxide and a gate electrode, the trench capacitor havingan inner electrode, an outer electrode and an insulating layer arrangedin between, comprising: providing a substrate with a trench; filling thetrench with a conductive trench filling to form the inner electrode ofthe trench capacitor; forming an insulating covering layer on theconductive trench filling; growing an epitaxial layer on the substrate,the epitaxial layer growing laterally, proceeding from the substrate,over the insulating covering layer, so that the epitaxial layer at leastpartly covers the insulating covering layer; forming a trench isolationin the epitaxial layer for the purpose of isolating adjacent memorycells; forming the first gate electrode on the epitaxial layer and asecond gate electrode for a passing word line on the trench isolation);introducing dopant to form the source region and the drain region, apredetermined thickness of the epitaxial layer and the doping beingchosen in such a way so that the source region reaches from the surfaceof the epitaxial layer that is remote from the substrate as far as theinsulation layer; etching a contact trench between the first gateelectrode and the second gate electrode, the epitaxial layer and theinsulating covering layer being removed from the region between thefirst gate electrode and the second gate electrode and the conductivetrench filling being uncovered and a sidewall of the epitaxial layerbeing uncovered; introducing a conductive contact into the contacttrench for the to electrically conductively connect the source region tothe conductive trench filling, a conductive connection being formedalong a length of the sidewall of the epitaxial layer, sad the lengthextending from the end of the sidewall formed at the covering layer asfar as the upper end of the conductive contact.
 11. The method accordingto claim 10, wherein characterized in that the epitaxial layer isthinned to a predetermined thickness.
 12. The method according to theepitaxial layer is thinned to a thickness of between
 25. 13. The methodaccording to claim 10, wherein the epitaxial layer, in order to bethinned, is partly oxidized to form an oxide layers, the oxide layer isbeing selectively removed selectively with respect to the remainder ofthe epitaxial layer.
 14. The method according to claim 10, wherein theepitaxial layer is thinned by means of chemical mechanical polishing.15. The method according to claim 10, wherein the oxidation of theepitaxial layer is carried out as wet oxidation at a temperature ofbetween 900° C. and 1100° C.
 16. The method according to claim 15,wherein the oxidation is carried out in an atmosphere containinghydrogen peroxide and hydrogen.
 17. The method according to claim 13,wherein the oxide layer is removed wet-chemically.
 18. The methodaccording to claim 10, wherein the surface of the conductive trenchfilling that is uncovered after the etching of the contact trench iscleaned, the surface being oxidized and the oxide layer formed in theprocess being removed.
 19. The method according to claim 10, wherein theconductive contact is formed by means of a selective deposition.
 20. Thesemiconductor memory according to claim 5, wherein the thickness of theepitaxial layer is between 40 nm and 80 nm.
 21. The semiconductor memoryaccording to claim 1, wherein an intermediate layer is formed in thecontact trench between the conductive trench filling and the conductivecontact from an insulating material having a thickness of up to 2nanometres, thereby enabling a tunnelling current through theintermediate layer.
 22. The semiconductor memory according to claim 1,wherein an intermediate layer is formed in the contact trench betweenthe conductive contact and the source region from an insulating materialhaving a thickness of up to 2 nanometres, thereby enabling a tunnellingcurrent through the intermediate layer.
 23. The method according toclaim 12, wherein the epitaxial layer is thinned to a thickness between40 nm and 80 nm.
 24. The method according claim 14, wherein theoxidation of the epitaxial layer (45) is carried out as wet oxidation ata temperature of between 900° C. and 1100° C.
 25. The method accordingto claim 24, wherein the oxidation is carried out in an atmospherecontaining hydrogen peroxide and hydrogen.